wafer (Total 69037 Patents Found)

Wafer (69037 Patents Found)
A method for producing a silicon single crystal in accordance with the Czochralski method. The single crystal is grown in an N 2 (V) region where a large amount of precipitated oxygen and which is located within an N region located outside an OSF ring region, or is grown in a region including the OSF ring region, N 1 (...
Embodiments of the invention comprise a new device and technique to realize an improved temperature control for a chemical photoresist developer utilizing a preexisting integrated single reservoir. This improvement is achieved by providing for a modified temperature control unit and procedure. The temperature control u...
A data management system for reviewing at least one layer of at least one semiconductor wafer is connected to a first inspection device and a second inspection device. The system includes a server which is connected to the first and second inspection devices. A review station is connected to the server. In use, the fir...
A method of water mark inspection. By forming a pattern on a test wafer, the water mark formed thereon directly reflects the features of a wafer product to be evaluated. The water mark is formed by simulating fabrication process conditions of forming the wafer product of which the performance is to be evaluated. Thus, ...
A method for manufacturing an SOI wafer. The method includes forming an oxide film on a surface of at least one silicon wafer of two silicon wafers. The method also includes bonding the silicon wafers through the oxide film at room temperature to form a room temperature bond end, one of the two silicon wafers being a b...
Embodiments of the invention are directed to methods and systems of purging of transfer containers, such as standardized mechanical interface (SMIF) pods. In particular, purified purge gases can purify front operated unified pods (FOUPs) and other non hermetically sealed transfer containers, such that the containers ca...
Disclosed is an MEMS device using an SOI wafer, the MEMS device comprising a first silicon layer, an insulation layer formed on the first insulation layer, a second silicon layer formed on the insulation layer, a protective layer formed on the second silicon layer, and a ground hole extending from an upper portion of t...
A wafer observation position designating apparatus and a wafer display position designating method for moving a wafer quickly to a desired observation position before the wafer surface is observed. The apparatus comprises imaging means for imaging the surface of a wafer, display means for displaying the image picked up...
There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×10 13 atoms/cm 3 or more, or with ...
The present invention relates to a method of producing an SOI wafer in which an SOI layer is formed on a buried oxide film by forming an oxide film on a surface of at least one of a bond wafer and a base wafer, bonding the bond wafer to the base wafer through the formed oxide film, and making the bond wafer into a thin...
The present invention relates to a method for forming monocrystalline silicon ingot and wafer. When forming a monocrystalline silicon ingot, melted silicon is introduced with a gas comprising deuterium atoms to receive the deuterium atoms at interstice sites, and thus the oxygen, carbon and other impurity contained the...
Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the...
New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds f...
An apparatus and method for assembling a large microbolometer infrared imaging array from sub-arrays, comprising the step of forming a sub-array assembly of independent imaging arrays on the silicon wafer as the imaging sensor is being processed, whereby seams or gaps in a resulting image are avoided....
The photosensitive adhesive composition of the invention comprises (A) an alkali-soluble resin, (B) an epoxy resin, (C) a radiation-polymerizable compound and (D) a photoinitiator, wherein the (D) photoinitiator contains at least (D1) a photoinitiator that exhibits a function which promotes polymerization and/or curing...
A method for manufacturing a piezoelectric film wafer includes a first processing step for carrying out an ion etching on a KNN piezoelectric film formed on a substrate by using a gas containing Ar, and a second processing step for carrying out a reactive ion etching by using a mixed etching gas containing a fluorine-b...
A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the...
A device for handling a substantially circular wafer is provided. The device includes an interior accessible through a plurality of entrances, and a plurality of sensors consisting of two sensors for each one of the plurality of entrances, each sensor capable of detecting a presence of the substantially circular wafer,...
One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been reloc...
Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first wi...
A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths ...
Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing...
System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-con...
A wafer cleaning device comprising a wafer stage for holding a wafer having a surface to be washed, a first nozzle positioned above the wafer, a second nozzle positioned above the wafer. A first height is between the first nozzle and the surface and a second height is between the second nozzle and the surface, wherein ...
Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first i...
A process instrument having a wafer-style body for mounting between an upstream flanged pipe and a downstream flanged pipe has a flow passage, a transmitter connected to the body, and first and second end plates fixed to the body. The first end plate has a first set of cams for engaging a plurality of threaded fastener...
A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface....
A handle wafer which prevents edge cracking during a thinning process and method of using the handle wafer for grinding processes are disclosed. The handle wafer includes a body portion with a bottom surface. A square edge portion is provided about a circumference of the bottom surface....